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Field-effect transistors (FETs) switched by quantum band-to-band tunneling (BTBT) mechanism, rather than conventional thermionic emission mechanism, are emerging as an exciting device candidate for future ultralow-power electronics due to their exceptional electronic properties of subthermionic subthreshold swing. However, fundamental limitations in drive current have hindered such technology encountering for high-performance and high-speed operations, especially for […]

We systematically fabricate devices and analyze data for vertical InAs/(In)GaAsSb nanowire tunnel field-effect transistors (TFETs), to study the influence of source dopant position and level on their device performance. The results show that delaying the introduction of dopants further in the GaAsSb source segments improved the transistor metrics (subthreshold swing (SS) and the on-current performance),

While magnetic random-access memories (MRAMs) are promising because of their nonvolatility, relatively fast speeds, and high endurance, there are major challenges in adopting them for the advanced technology nodes. One of the major challenges in scaling MRAM devices is caused by the ever-increasing resistances of interconnects. In this article, we first study the impact of

Resistive in-memory computing (IMC) architectures currently lag behind SRAM IMCs and digital accelerators in both energy efficiency and compute density due to their low compute accuracy. This article proposes the use of signal-to-noise-plus-distortion ratio (SNDR) to quantify the compute accuracy of IMCs and identify the device, circuit, and architectural parameters that affect it. We further

The design of LDMOS (Lateral double diffused metal oxide semiconductor) devices with CFP (Contact field plate) has been of great significance in recent years, according to its advantages of low resistance and high switch efficiency. In this paper, this ultra-low $R_{mathrm{ on,sp}}$ (Specific on-resistance) LDMOS device is simulated, designed, and fabricated. The effects on FOM

Self-organizing Map (SOM) neural network is a prominent algorithm in unsupervised machine learning, which is widely used for data clustering, high-dimensional visualization, and feature extraction. However, the hardware implementation of SOM is limited by the von Neumann bottleneck. Herein, a SOM neural network is implemented by the combination of 3D NAND flash memory arrays and

A performance evaluation of cryogenic CMOS circuit at liquid-helium temperature (4.2K) is conducted using a standard 65nm bulk CMOS for quantum state controller (QSC) applications. The ON-current (Ion) of the core n/pMOSFET are increased by 25% and 9% with excellent gate modulation (Ion/Ioff= $sim 10~^{mathrm{ 9}}$ ). The cryogenic characteristics of copper interconnects in the

In this work, vertical gallium nitride (GaN) trench Junction Barrier Schottky (JBS) diodes fabricated with a novelty slanted p-GaN sidewall on a 2-inch free-standing GaN (FS-GaN) substrate were demonstrated. The slanted sidewall on edge of devices was conducted to suppress the peak of electric field distributions at high voltage. By realizing an off-state breakdown voltage

In this paper, an integrated device which realized the dual-mode integration of power amplifier (PA) and radio frequency (RF) switch based on GaN dual-gate (DG) structure is designed and fabricated. The integrated device provides two working modes and meets the performance requirements of PA and RF switch. In the transmit (Tx) mode, the integrated device

Lack of transparent contacts has been a critical bottleneck for the two-dimensional Transition Metal Dichalcogenides (TMDs) Field Effect Transistors (FETs). In the absence of approaches to introduce physical doping without inducing crystal damage, charge transfer-based doping has been widely adopted. This manuscript presents a unique charge transfer doping technique using potassium iodide (KI) solution for